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GPUpd: A Fast and Scalable Multi-GPU Architecture Using Cooperative Projection and Distribution

Title
GPUpd: A Fast and Scalable Multi-GPU Architecture Using Cooperative Projection and Distribution
Authors
Kim, YoungsokJO, JAEEONJANG, HANHWIRHU, MINSOOKIM, HANJUNKim, Jangwoo
Date Issued
2017-10-18
Publisher
IEEE/ACM
Abstract
Graphics Processing Unit (GPU) vendors have been scaling single-GPU architectures to satisfy the ever-increasing user demands for faster graphics processing. However, as it gets extremely difficult to further scale single-GPU architectures, the vendors are aiming to achieve the scaled performance by simultaneously using multiple GPUs connected with newly developed, fast inter-GPU networks (e.g., NVIDIA NVLink, AMD XDMA). With fast inter-GPU networks, it is now promising to employ split frame rendering (SFR) which improves both frame rate and single-frame latency by assigning disjoint regions of a frame to different GPUs. Unfortunately, the scalability of current SFR implementations is seriously limited as they suffer from a large amount of redundant computation among GPUs. This paper proposes GPUpd, a novel multi-GPU architecture for fast and scalable SFR. With small hardware extensions, GPUpd introduces a new graphics pipeline stage called Cooperative Projection & Distribution (C-PD) where all GPUs cooperatively project 3D objects to 2D screen and efficiently redistribute the objects to their corresponding GPUs. C-PD not only eliminates the redundant computation among GPUs, but also incurs minimal inter-GPU network traffic by transferring object IDs instead of mid-pipeline outcomes between GPUs. To further reduce the redistribution overheads, GPUpd minimizes inter-GPU synchronizations by implementing batching and runahead-execution of draw commands. Our detailed cycle-level simulations with 8 real-world game traces show that GPUpd achieves a geomean speedup of 4.98X in single-frame latency with 16 GPUs, whereas the current SFR implementations achieve only 3.07X geomean speedup which saturates on 4 or more GPUs.
URI
https://oasis.postech.ac.kr/handle/2014.oak/42832
Article Type
Conference
Citation
International Symposium on Microarchitecture, 2017-10-18
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김한준KIM, HANJUN
Dept. Convergence IT Engineering
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