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dc.contributor.author김영환-
dc.contributor.author김태훈-
dc.contributor.author김욱-
dc.contributor.author김진욱-
dc.date.accessioned2018-05-23T14:42:03Z-
dc.date.available2018-05-23T14:42:03Z-
dc.date.created2010-05-06-
dc.date.issued2009-12-16-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/45850-
dc.publisherISIC-
dc.relation.isPartOfThe 12th International Symposium on Integrated Circuits (ISIC-2009)-
dc.relation.isPartOfTHE 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC-2009)-
dc.titleHigh-level Statistical Timing Analysis under Process Variation-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitationThe 12th International Symposium on Integrated Circuits (ISIC-2009)-
dc.citation.conferenceDate2009-12-14-
dc.citation.conferencePlaceSI-
dc.citation.titleThe 12th International Symposium on Integrated Circuits (ISIC-2009)-
dc.contributor.affiliatedAuthor김영환-
dc.contributor.affiliatedAuthor김태훈-
dc.contributor.affiliatedAuthor김욱-
dc.contributor.affiliatedAuthor김진욱-
dc.description.journalClass1-
dc.description.journalClass1-

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김영환KIM, YOUNG HWAN
Dept of Electrical Enginrg
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