Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware
SCIE
SCOPUS
- Title
- Input Voltage Mapping Optimized for Resistive Memory-Based Deep Neural Network Hardware
- Authors
- Kim, Taesu; HYUNGJUN, KIM; Kim, Jinseok; Kim, Jae-Joon
- Date Issued
- 2017-09
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- Artificial neural network (ANN) computations based on graphics processing units (GPUs) consume high power. Resistive random-access memory (RRAM) has been gaining attention as a promising technology for implementing power-efficient ANNs, replacing GPU. However, nonlinear I-V characteristics of RRAM devices have been limiting its use for ANN implementation. In this letter, we propose a method and a circuit to address issues due to the nonlinear I-V characteristics. We demonstrate the feasibility of the method by simulating its application to multiple neural networks, from multi-layer perceptron to deep convolutional neural network based on a typical RRAM model. Results from classifying datasets including ImageNet show that the proposed method produces much higher accuracy than the naive linear mapping for a wide range of nonlinearity.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/50568
- DOI
- 10.1109/LED.2017.2730959
- ISSN
- 0741-3106
- Article Type
- Article
- Citation
- IEEE ELECTRON DEVICE LETTERS, vol. 38, no. 9, page. 1228 - 1231, 2017-09
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- There are no files associated with this item.
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