3.8 mW 10 Gbit/s CDR for intra-panel interface with a modulated training pattern

Abstract

A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electro-magnetic interference characteristics can be improved over the conventional training pattern. A phaselocked loop-based CDR circuit with the proposed scheme in a 65 nm CMOS technology is designed. The measured lock range was between 6 and 10 Gbit/s and the power efficiency was 0.38 mW/Gbit/s at 10 Gbit/s inputs.