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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 심재윤 | - |
| dc.contributor.author | 박승진 | - |
| dc.contributor.author | 하현수 | - |
| dc.contributor.author | 서윤재 | - |
| dc.contributor.author | 박홍준 | - |
| dc.date.accessioned | 2018-06-15T06:20:23Z | - |
| dc.date.available | 2018-06-15T06:20:23Z | - |
| dc.date.created | 2009-03-23 | - |
| dc.date.issued | 2008-11-04 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/51123 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE Asian Solid-State Circuits Conference | - |
| dc.relation.isPartOf | ASSCC | - |
| dc.title | A Transister-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE Asian Solid-State Circuits Conference | - |
| dc.citation.conferencePlace | JA | - |
| dc.citation.title | IEEE Asian Solid-State Circuits Conference | - |
| dc.contributor.affiliatedAuthor | 심재윤 | - |
| dc.contributor.affiliatedAuthor | 박승진 | - |
| dc.contributor.affiliatedAuthor | 하현수 | - |
| dc.contributor.affiliatedAuthor | 서윤재 | - |
| dc.contributor.affiliatedAuthor | 박홍준 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg