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A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture
- Title
- A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture
- Authors
- 심재윤
- Date Issued
- 2001-02-07
- Publisher
- IEEE
- Article Type
- Conference
- Citation
- International Solid-State Circuit Conference, page. 378 - 379, 2001-02-07
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- 심재윤SIM, JAE YOON
- Dept of Electrical Enginrg