Conference
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김장우 | - |
| dc.date.accessioned | 2018-06-17T09:53:42Z | - |
| dc.date.available | 2018-06-17T09:53:42Z | - |
| dc.date.created | 2011-02-27 | - |
| dc.date.issued | 2009-03-25 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/56879 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE Workshop On Silicon Error in Logic - System Effects | - |
| dc.relation.isPartOf | PROCEEDINGS OF IEEE WORKSHOP ON SILICON ERROR IN LOGIC - SYSTEM EFFECTS | - |
| dc.title | Modeling SRAM Failure Rates to Enable Fast, Dense, Low-Power Caches | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE Workshop On Silicon Error in Logic - System Effects | - |
| dc.citation.conferenceDate | 2009-03-24 | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.title | IEEE Workshop On Silicon Error in Logic - System Effects | - |
| dc.contributor.affiliatedAuthor | 김장우 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 김장우KIM, JANGWOO
- Dept of Computer Science & Enginrg