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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김영환 | - |
| dc.contributor.author | 김재훈 | - |
| dc.date.accessioned | 2018-06-17T10:17:29Z | - |
| dc.date.available | 2018-06-17T10:17:29Z | - |
| dc.date.created | 2011-03-25 | - |
| dc.date.issued | 2010-08-04 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/57303 | - |
| dc.publisher | Asqed | - |
| dc.relation.isPartOf | Asia Symposium on Quality Electronic Design(Asqed) 2010 | - |
| dc.relation.isPartOf | ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | - |
| dc.title | Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | Asia Symposium on Quality Electronic Design(Asqed) 2010, pp.314 - 317 | - |
| dc.citation.conferenceDate | 2010-08-03 | - |
| dc.citation.conferencePlace | MY | - |
| dc.citation.endPage | 317 | - |
| dc.citation.startPage | 314 | - |
| dc.citation.title | Asia Symposium on Quality Electronic Design(Asqed) 2010 | - |
| dc.contributor.affiliatedAuthor | 김영환 | - |
| dc.contributor.affiliatedAuthor | 김재훈 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 김영환KIM, YOUNG HWAN
- Dept of Electrical Enginrg