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dc.contributor.author최경진en_US
dc.date.accessioned2015-02-24T15:13:03Z-
dc.date.available2015-02-24T15:13:03Z-
dc.date.issued2001en_US
dc.identifier.otherOAK-2015-03711en_US
dc.identifier.urihttp://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001905863en_US
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/6091-
dc.descriptionDoctoren_US
dc.languagekoren_US
dc.publisher포항공과대학교en_US
dc.rightsBY_NC_NDen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/2.0/kren_US
dc.title표면 결함 및 내부 트랩이 전계 효과 소자의 전기적 특성에 미치는 영향en_US
dc.title.alternativeEffects of surface states and bulk traps on electrical properties of field effect transistorsen_US
dc.typeThesisen_US
dc.contributor.college일반대학원 신소재공학과en_US
dc.date.degree2001-02en_US
dc.type.docTypeThesis-

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