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A Dual-Retention Time Architecture towards Secure and High Performance STT-RAM Main Memory Subsystem

Title
A Dual-Retention Time Architecture towards Secure and High Performance STT-RAM Main Memory Subsystem
Authors
이승구이태민유승주
Date Issued
2014-02-25
Publisher
한국반도체연구조합
URI
https://oasis.postech.ac.kr/handle/2014.oak/65750
Article Type
Conference
Citation
한국반도체학술대회, 2014-02-25
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유승주YOO, SUNGJOO
Dept of Electrical Enginrg
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