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USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

Title
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling
Authors
박홍준성기환임지훈김병섭심재윤
Date Issued
2014-05-17
Publisher
대한전자공학회
URI
https://oasis.postech.ac.kr/handle/2014.oak/67938
Article Type
Conference
Citation
2014년 SoC 학술대회, 2014-05-17
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김병섭KIM, BYUNGSUB
Dept of Electrical Enginrg
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