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3D Simulation of Threshold Voltage Variations Due to Random Grain Boundary and Discrete Dopants in Sub-20 nm Gate-All-Around Poly-SiTransistor

Title
3D Simulation of Threshold Voltage Variations Due to Random Grain Boundary and Discrete Dopants in Sub-20 nm Gate-All-Around Poly-SiTransistor
Authors
백창기
Date Issued
2014-02-25
Publisher
한국반도체학술대회
URI
https://oasis.postech.ac.kr/handle/2014.oak/68456
Article Type
Conference
Citation
제21회 한국반도체학술대회, 2014-02-25
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