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Impact of High-ĸ Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node
- Title
- Impact of High-ĸ Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node
- Date Issued
- 2014-09-09
- Publisher
- Japanese Journal of Applied Physics
- Article Type
- Conference
- Citation
- 2014 International Conference on Solid State Devices and Materials, 2014-09-09
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Related Researcher
- 정윤하JEONG, YOON HA
- Dept of Electrical Enginrg