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A 1.35Gbps Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with 2X Over-sampling Phase Detector for Skew Compensation between Clock and Data
- Title
- A 1.35Gbps Decision Feedback Equalizing Receiver for the SSTL SDRAM Interface with 2X Over-sampling Phase Detector for Skew Compensation between Clock and Data
- Authors
- 박홍준
- Date Issued
- 2002-08-01
- Publisher
- IDEC
- Article Type
- Conference
- Citation
- IDEC Conference, 2002-08-01
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg