Optimization of 70 nm nMOSFET performance using gate layout
- Title
- Optimization of 70 nm nMOSFET performance using gate layout
- Authors
- 정윤하
- Publisher
- IEEK
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/88192
- Article Type
- Conference
- Citation
- IEEK Summer Conference 2006, page. 581 - 582
- Files in This Item:
- There are no files associated with this item.
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