Thesis
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 여동희 | en_US |
| dc.date.accessioned | 2014-12-01T11:46:54Z | - |
| dc.date.available | 2014-12-01T11:46:54Z | - |
| dc.date.issued | 2010 | en_US |
| dc.identifier.other | OAK-2014-00394 | en_US |
| dc.identifier.uri | http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000000791867 | en_US |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/896 | - |
| dc.description | Master | en_US |
| dc.description.abstract | This paper presents a receiver and a transmitter digital circuit for the USB 2.0 physical layer high speed interface. The circuit operates in 480 Mbit/sec. The receiver consists of a 1-to-8-bit de-serializer, a bit un-stuffer, and a non-return to zero inverted decoder. The transmitter includes an 8-to-1-bit serializer, a bit stuffer, and a non-return to zero inverted decoder. Squelch signal is added to a basic USB 2.0 system for a safe operation of the circuit, and other functions are fully verified USB 2.0 specification. Synthesis, and auto post and routing process are performed with 130 nm process. | en_US |
| dc.language | kor | en_US |
| dc.publisher | 포항공과대학교 | en_US |
| dc.rights | BY_NC_ND | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/2.0/kr | en_US |
| dc.title | Verilog로 설계 및 합성한 USB 2.0 High Speed용 송수신기의 디지털 회로 | en_US |
| dc.type | Thesis | en_US |
| dc.contributor.college | 일반대학원 전자전기공학부 | en_US |
| dc.date.degree | 2010- 8 | en_US |
| dc.type.docType | Thesis | - |
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