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A study on Selector Devices for High-Density Memory Application

Title
A study on Selector Devices for High-Density Memory Application
Authors
Chekol, Solomon Amsalu
Date Issued
2018
Publisher
포항공과대학교
Abstract
Emerging non-volatile memories―such as resistive switching RAM, phase change memories, ferroelectric RAM, STT-MRAM―are studied extensively as a potential candidate for future high-density memory application owing to their simple 2 terminal structure, better scalability, and low power consumption. In order to achieve such high-density memory, a cross-point array structure, in which writing/erasing or reading of the desired (selected cell) can be done by applying a voltage at the edge of the array, has been introduced and investigated widely. In cross point array, it is critical to delivering the necessary power and current to the selected cell while avoiding any unnecessary perturbation to the unselected cell. To do that, a selector device is required in order to suppress sneak path current, undesired current flow through the unselected cell, during operation. Highly non-linear selectors are ideal to prevent such unwanted current from flowing through the unselected cell. The high resistance at low bias can effectively inhibit the sneak current while the low resistance at high bias can supply sufficient current to write/read or erase the adjacent selected memory cell. Insulator-to-metal transition (IMT) - and Ovonic threshold switching (OTS) based-selectors are the most promising selector devices for cross-point memory array owing to their fast, uniform and abrupt high resistance to low resistance transition. However, IMT based selectors are suffering from high off-state current which tackles their functionality for low power device application. Similarly, the realization of OTS based selector devices is hindered by their material complexity and thermal stability problem. This thesis explores the issues and solutions for the aforementioned two type of selector devices. In chapter three, the origin of the high off-state current of NbO2 investigated. Grain boundaries and local sub-stoichiometric (NbO2-x) regions are found to be mainly responsible for the high leakage current. By comparing sputtered NbO2 film on a substrate and thermally grown NbO2 film on polycrystalline Nb wire, it is found that the off-current of the thermally grown film was lower than the sputter deposited film. This off-current reduction could be explained by the less contribution of grain boundary leakage owing to the relatively large grain size of the polycrystalline Nb wire. Similarly, better stoichiometric NbO2 could be formed in the thermally grown film. On contrary, the sputter deposited film which has a small grain size and off-stoichiometry shows higher leakage current. In addition, the leakage conduction paths and grain size effects are studied by using Conductive Atomic Force Microscopy (CAFM) and supported by Simulations. Furthermore, by introducing a leakage passivation layer of 15nm HfO2, further reduction of the off-current is achieved. In chapter four, a new C-Te based binary Ovonic Threshold Switching (OTS) selector device is introduced. The proposed device is scalable down to Ø30nm and exhibits excellent performance and thermal stability. High selectivity (on/off ratio >105), extremely low off-current (~1nA), superfast switching speed of <10ns (with a transition time of <2ns and delay time of <8ns), and high endurance of 109 are some of the characteristics of this selector device. The high thermal stability of our device can be explained by the atomic size difference between the two elements, Te and C. Thermal stability failure of binary OTS films is mainly related to the segregation and crystallization of Te atoms in the OTS film. However, the relatively small atomic size of C, compared to Te, can effectively inhibit this segregation and crystallization of Te, thus improving the thermal stability of the film. Furthermore, the functionality of the proposed selector is evaluated by 1S1R integration by serially connecting the selector device with a ReRAM device. The 1S-1R integrated device exhibits a successful suppression of leakage current at the half-selected cell and shows excellent read-out margin (>212 word lines) in a fast read operation.
URI
http://postech.dcollection.net/common/orgView/200000103860
https://oasis.postech.ac.kr/handle/2014.oak/93123
Article Type
Thesis
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