채널신호 변동전압이 40mV인 TSV와 PCB 전송선용 저전력 고속 송수신 회로

Abstract

Two transceiver circuits are proposed for low-power high-speed transmission by reducing the channel-signal-swing to 40mV; one is a single-ended transceiver circuit for an on-chip through-silicon via (TSV) channel and the other is a differential transceiver circuit for a 12” FR-4 channel. First, the single-ended transceiver circuit for on-chip TSV channel employs a switched-diode termination (SDT). The channel signal swing is limited to 40 mV by the SDT to reduce the transmitter (TX) power without short-circuit current loss of the center-tap resistor termination. An inverter-cascade amplifier is used to reduce the receiver (RX) power. Inverter feedback is applied to the cascade amplifier of the RX to increase the bandwidth from 0.9 to 5.0 GHz. The transceiver in the 65-nm CMOS process combined with an emulated five-stack TSV on the same chip works at 8 Gb/s with 149 fJ/b/pF and a 1.2-V supply. Second, the differential transceiver circuit has 40mVppd channel signal-swing, 9mVppd receiver (RX) input sensitivity, and 0.59pJ/b energy efficiency at 9Gb/s with a 12” FR-4 channel. A current-integrating TIA (CI-TIA) is used as a RX pre-amplifier to enhance the RX input sensitivity by increasing the voltage gain of the CI-TIA to around 18 at 9Gb/s. A voltage-mode pre-emphasis equalizer is combined with a current-mode logic (CML) driver at transmitter (TX) to save the low-frequency de-emphasis current of the conventional current-mode equalizer combined with a CML driver. The voltage-mode equalizer consists of a series connection of an inverter and a capacitor; the equalization coefficient is proportional to the supply voltage of the inverter. The transceiver chip in a 65nm CMOS process consumes 2.8mW at TX and 2.5mW at RX with a 1V supply and a 12” FR-4 channel at 9Gb/s.