A Study on Device Design for Gate-All-Around Si-Nanowire FETs

Abstract

Gate-all-around nanowire field effect transistors (GAA NWFETs) have been considered as promising replacements of fin-based field effect transistors (FinFETs) for sub-10 nm technology node. Despite of high on/off current ratio and excellent gate controllability, there still remain unresolved issues such as parasitic resistance (RSD) and parasitic capacitance (Cpara) for the continuous scaling. Therefore, it is important to minimize these parasitic effects and optimize the design parameters for better DC/AC performances. In this study, geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara) have been quantitatively evaluated using well-calibrated TCAD simulations and analytic RC models, and then proposed optimized structure of GAA NWFETs. First, the RSD reduction technique with high-k materials is suggested in order to improve the drive current of NWFETs. For various spacer materials, the RSD components such as spreading resistance (RSP), extension resistance (REXT), interface resistance (RINT), deep source and drain resistance (RDP), and contact resistance (RCON) are extracted by analytic models. It is found that the most effective way to reduce RSD is the reduction of REXT which is the dominant components of RSD. When using high-k materials for spacer, the fringe electric field and the electron concentration accumulated in the extension region increase significantly in the operational regime of devices. Thus, the REXT decrease from the reduced effective resistivity in the extension region, and this contributes to reducing the RSD. High-k spacers can enhance the immunity of short channel effects as well as improve the drive current of NWFETs by decreasing the RSD. Although, high-k spacer definitely improves drive current of NWFETs with the RSD reduction, it can significantly increase the Cpara leading to degradation of AC performances. Therefore, it is imperative to consider the trade-off between the RSD and Cpara when designing the NWFETs. Next, an optimized design has been proposed for various figures-of merit (FOMs), particularly the current-gain cutoff frequency and the gate delay (CV/I), in terms of the spacer dielectric constant (ksp), the extension length (LEXT), the nanowire diameter (Dnw), and the operation voltage (VDD). Geometry-dependent optimal values of ksp with different VDD are proposed and it is found that as the LEXT and VDD decrease and the Dnw increases, the optimal ksp value shifts from high-k to low-k regime. However, unlike fT, an excessively low ksp is unacceptable and adopting a shorter LEXT and a larger Dnw is the most effective way for reducing the device delay. Finally, the Fin-like GAA NWFETs has been proposed for 5 nm node technology node. Geometry dependent device performance of Fin-like GAA NWFETs are investigated using the well-calibrated simulation, and it is found that the underlap with high-k spacer structures are effective in that underlap structures are favorable for device scaling with reduced Cpara and high-k spacers significantly decrease RCH. Effects of fin height (Hfin) on electrostatic of GAA NWFETs are also analyzed. Gate controllability improves as the Hfin decreases indicating that shrinking fin width (Wfin) is not the only way to improve gate controllability. From Fin-like GAA NWFETs, it will be expected to get out of tough process margin of Wfin in conventional Si-FinFETs and have higher drive current than that of circular NWFETs.