All-Synthesizable Transceiver for USB2.0 Interface
- Title
- All-Synthesizable Transceiver for USB2.0 Interface
- Authors
- 성기환
- Date Issued
- 2017
- Publisher
- 포항공과대학교
- Abstract
- The transceiver for USB2.0 interface was designed with Verilog and synthesized to enhance design portability. The proposed transceiver includes SerDes, transmitter driver, receiver frontend, data recovery circuit and 5-phase phase-locked loop (PLL). The transmitter driver employs a differential current-mode architecture with a variable output voltage swing and includes a pre-driver. The 5-phase phase-locked was implemented by adding a coarse phase detector_2 to a conventional counter-based digital PLL. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The transceiver satisfies the USB2.0 eye-mask specification in the measured eye diagrams and the data recovery circuits gives a measured BER less than 1E-12 with PRBS 2E31-1 data. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively. The transceiver consumes 27 mW at 1.2 V supply. The transceiver chip in a 65-nm process occupies 0.13 mm2.
- URI
- http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002324481
https://oasis.postech.ac.kr/handle/2014.oak/93304
- Article Type
- Thesis
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.