Solution-Processed Complementary Organic Field-Effect Transistors with Patterning-Free Device Geometry

Abstract

This work suggests structural solutions for complicated patterning processes in fabricating complementary organic field-effect transistors (COFETs) and circuits. The goal of this work is demonstrating COFETs without patterning complementary organic semiconductors (OSCs) and verifying and understanding electrical operation of the COFETs. The planar-type COFETs were simply integrated by dividing n and p type OSCs with sandwiched gate-dielectric layer in between two OSC layers without further pattering techniques. Depending on contact configurations with respect to the OSC layer, four-types of common-dielectric COFETs consisting of a top-gate n-type OSC, poly{[N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bithiophene)}, field-effect transistor and a bottom-gate p-type OSC, poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2-yl)thieno [3,2-b]thiophene)], filed-effect transistor were fabricated. The common-dielectric COFET with a bottom contact n-type OFET and a top-contact p-type OFET (BNTP) achieved highest carrier mobilities, electron mobility (μn) of 1.33×10-2 cm2∙V−1∙s−1 and hole mobility (μp) of 4.27×10-2 cm2∙V−1∙s−1, because both COFETs had staggered configurations. Characteristic parameters of the BNTP common-dielectric COFET were hardly affected by existence of the OSC layers between the gate electrode and the dielectric layer except for the threshold voltage shift. In the inverter operation, the maximum static voltage gain was 25 V/V, and the static noise margin was 55 % at VDD = 30 V. Next, flexible three-dimensional COFETs were fabricated by solution processing at low temperature without patterning OSCs. In the transistor-on-transistor structure that removes the electrical interferences between transistors, a bottom-gate top-contact p-type organic field effect transistor was stacked on top of a top-gate bottom-contact contact n type organic field-effect transistor with a gate shared between the two. The organic field effect transistor with a poly [2,5-bis (7-decylnonadecyl) pyrrolo [3,4-c]pyrrole-1,4(2H,5H)-dione-(E)- 1,2-bis(5-(thiophen-2-yl) selenophen-2-yl)ethene], p-type OSC, had the μp of 0.42 cm2∙V−1∙s−1 and the organic field-effect transistor with a poly[( E )-2,7-bis(2-decyltetradecyl)-4-methyl-9-(5-(2-(5-methylthiophen-2-yl)vinyl)thiophen-2-yl)benzo[lmn][3,8] phenanthroline-1,3,6,8(2 H ,7 H )-tetraone], n type OSC, had the μn of 0.20 cm2∙V−1∙s−1. In the inverter operation, the maximum static voltage gain was 15 ± 1 V/V, and the static noise margin was 60 % at VDD = 30 V. The proper selection of gate dielectric materials enabled 3D-COFETs that had been solution processed at 110 °C to obtain hysteresis-free electrical characteristics. These structural approaches for simplifying integration of COFETs without patterning OSCs are expected to reduce both footprint and production costs of flexible organic electronics, and achieve high-density organic circuit.