A 10-GHz Multi-Purpose Reconfigurable Built-in Self-Test Circuit for High-Speed Links

Abstract

This thesis presents a multi-purpose built-in self-test circuit to reduce large design overhead in preparing various tests of high-speed links. The proposed circuit can be configured as a pattern generator, a pseudo-random bit sequence generator, a scrambler, a descrambler, or a snapshot, all of which are frequently used in various link tests but also require significant design effort. To reduce the large design overhead, we efficiently implemented the five aforementioned functions in a single design by sharing their common structure. A test chip was fabricated in 28-nm CMOS technology, and the five target functions were successfully verified at 10Gb/s consuming 9.27 mW. To demonstrate the usefulness of the proposed circuit, a horizontal eye and a pulse-response were also measured in-situ by utilizing the proposed circuits which were configured to conduct various different functions.