Real-Time Pedestrian Detection in 60 fps Video on FPGA

Abstract

This paper presents a real-time pedestrian detection hardware architecture on Field Programmable Gate Arrays (FPGAs). This architecture uses Histograms of Oriented Gradients (HOG) descriptor and Support Vector Machine (SVM) for classifier. We designed a norm and arctangent calculator, using a formula of trigonometric function leading to low loss of detection rate and high efficiency of resource usage. HOG modules of all scales share SVM module, this design uses resources efficiently. We could process 60 images (1024 x 768 pixels) per second at 10 scales with a latency of < 200 μs. We could apply this hardware system to many areas including self-driving cars, autonomous robot navigation.