A Study on Simulation and Characterization of Advanced Si Nano-devices and Applications

Abstract

Bulk FinFETs have been successfully scaled down to 14-nm technology node by adapting rectangular fin structure and air-gap materials at back-end-of-line levels. According to 2013 ITRS roadmap, however, logic transistors in 7 nm technology node would be suffered from severe impacts of parasitic resistances and capacitances on DC/AC performances and variability concerns such as random dopant fluctuation, line edge roughness, and work-function variation. In this study, parasitic components and variability problems of nanoscale FETs have been characterized and analyzed. DC/AC characteristics of Si bulk FinFETs including transistor and middle-of-line levels are precisely investigated using fully-calibrated three-dimensional device simulations for system-on-chip applications. Scaling fin widths down to 5 nm enhances gate-to-channel controllability and improves RC delay, but a critical increase in band-to-band tunneling currents from source to drain can hardly satisfy low-power application limits in the 7-nm node. All lightly-doped extension regions as a solution may decrease band-to-band tunneling currents and total gate capacitances because of better short channel immunity and lower parasitic capacitances, respectively. Using a systematic TCAD-based RC calculation, overlap/underlap lengths in the 7-nm node FinFETs have been optimized. Impacts of random dopant fluctuations on Si nanowire FETs have been investigated in terms of different diameters and extension lengths. Decreasing diameters of nanoscale FETs can cause significant random dopant fluctuations at the extension regions. Si Nanowire FETs with smaller diameter and longer extension length can reduce average values and variations of subthreshold swing and drain-induced barrier lowering, which can improve short channel immunity. Standard deviations of drain currents can decrease greatly as extension length increases due to decreasing the number of arsenic dopants penetrating into channel region. To understand variability origins of drain currents, variations of extension resistance and low-field mobility are evaluated. Both of these two parameters can cause variations of drain currents. Si nanowire FETs with sufficient extension lengths and large cross-sections are preferential to achieve short channel immunity and small variations of DC characteristics. Many researchers have focused on new material-based FETs such as group III-V, carbon nanotube, and 2D materials such as MoS2 and graphene or Si-based FETs with alternative device structure. In case of Si-based FETs, vertical nanowire structure is one of the possible candidates to substitute bulk FinFETs due to higher device density, smaller parasitic elements, and CMOS compatibility. However, top-down fabrication can induce difference of structure and doping concentrations between top-side and bottom-side vertical nanowires causing variation of DC characteristics. Vertical Si nanowire FETs with different diameters and underlap lengths are investigated. Source-side diameters can determine on-state characteristics and drain-induced barrier lowering, whereas drain-side diameters can control band-to-band tunneling currents during off-state conditions. Si nanowire FETs with short drain-side underlap lengths decrease drain-side extension resistance but degrade off-state characteristics due to large bandgap narrowing effects at drain extension regions. Proper device design of vertical Si nanowire FETs have been proposed to improve both drain current on/off ratio and short channel characteristics.