DC Field | Value | Language |
---|---|---|
dc.contributor.author | KIM, HANJOON | - |
dc.contributor.author | KIM, GWANGSUN | - |
dc.contributor.author | KIM, JOHN | - |
dc.date.accessioned | 2018-12-04T02:57:53Z | - |
dc.date.available | 2018-12-04T02:57:53Z | - |
dc.date.created | 2018-11-12 | - |
dc.date.issued | 2012-06-04 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/94460 | - |
dc.description.abstract | While much research has been done using 2D mesh network as a baseline on-chip network topology, recent multi-core chips from vendors leverage a ring topology. In this work, we re-visit the topology comparison in on-chip networks and model the impact of on-chip network on overall performance while holding the entire chip power constant. We vary the amount of power allocated to the on-chip network and evaluate its impact on overall performance to determine a balanced system design. We show how the ring topology is efficient in current technology at 45nm but the scalability is limited as technology continues to scale and show how a simple hierarchical ring approach can provide a scalable solution. | - |
dc.language | English | - |
dc.publisher | IEEE Computer Society | - |
dc.relation.isPartOf | 3rd International Green Computing Conference | - |
dc.relation.isPartOf | Proceedings of the 3rd International Green Computing Conference | - |
dc.title | Scalable on-chip network in power constrained manycore processors | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 3rd International Green Computing Conference | - |
dc.citation.conferenceDate | 2012-06-04 | - |
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | San Jose, CA, USA | - |
dc.citation.title | 3rd International Green Computing Conference | - |
dc.contributor.affiliatedAuthor | KIM, GWANGSUN | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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