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Cited 5 time in webofscience Cited 5 time in scopus
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dc.contributor.authorGi, Sang-Gyun-
dc.contributor.authorYeo, Injune-
dc.contributor.authorChu, Myonglae-
dc.contributor.author문기봉-
dc.contributor.authorHwang, Hyunsang-
dc.contributor.authorLee, Byung-Geun-
dc.date.accessioned2019-04-07T16:53:08Z-
dc.date.available2019-04-07T16:53:08Z-
dc.date.created2018-09-18-
dc.date.issued2018-09-
dc.identifier.issn0018-9383-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/95679-
dc.description.abstractThis paper presents a new method for modeling the nonideal conductance response (CR) of synaptic devices. Unlike previous studies, which utilize physical device properties for modeling, this paper only uses the measured CR data. This allows the proposed modeling method to be easily applied to various types of synaptic devices without considering the unique physical properties of each device. An efficient piecewise linear approximation method which offers a tradeoff between computational complexity and simulation accuracy of neural networks is also presented to generate a linear device model out of nonlinear CR data. In addition, model parameters, which reflect the nonideal characteristics of the CR such as abrupt and asymmetric conductance changes, conductance variation, and limited conductance dynamic range, are introduced to evaluate the network performances in the presence of the nonidealities. By adjusting the model parameters, the desired CR satisfying the network performance requirements can be derived for device development. A three-layer neural network employing the device model has been designed and trained for the MNIST data set in order to demonstrate the application of the model to system-level simulations and verify the effectiveness of the modeling method.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.titleModeling and System-Level Simulation for Nonideal Conductance Response of Synaptic Devices-
dc.typeArticle-
dc.identifier.doi10.1109/TED.2018.2858762-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.9, pp.3996 - 4003-
dc.identifier.wosid000442357000058-
dc.citation.endPage4003-
dc.citation.number9-
dc.citation.startPage3996-
dc.citation.titleIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.volume65-
dc.contributor.affiliatedAuthor문기봉-
dc.contributor.affiliatedAuthorHwang, Hyunsang-
dc.identifier.scopusid2-s2.0-85050974048-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.type.docTypeArticle-
dc.subject.keywordPlusNEURAL-NETWORK-
dc.subject.keywordPlusMEMRISTOR-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusRECOGNITION-
dc.subject.keywordAuthornonvolatile memory-
dc.subject.keywordAuthorsynaptic device-
dc.subject.keywordAuthorsystem-level simulation-
dc.subject.keywordAuthorConductance response (CR)-
dc.subject.keywordAuthordevice modeling-
dc.subject.keywordAuthormemristor-
dc.subject.keywordAuthorMNIST-
dc.subject.keywordAuthorneural networks-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-

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황현상HWANG, HYUNSANG
Dept of Materials Science & Enginrg
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