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Calculating the probability of timing violation of F/F-controlled paths with timing variations SCOPUS

Title
Calculating the probability of timing violation of F/F-controlled paths with timing variations
Authors
Kwon, H.-J.Kim, Y.H.
Date Issued
2017-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
We propose an analytic method to calculate the probability of timing violation of F/F-controlled paths by considering timing variations. We first characterize the timing characteristics of F/Fs and path delays using a generalized canonical delay model. The probability of setup-time violation is then calculated by considering the correlation between F/Fs and logic paths. For the calculation, we used conditional tightness probability equation which reflects the nonlinearity of the process parameters. In experiments, the proposed method exhibited the error less than 7 % with respect to Monte-Carlo (MC) simulation results. Compared to the benchmark method that does not consider the variations of the timing characteristics of F/Fs, the proposed method improved the accuracy by more than 18% on average. ? 2016 IEEE.
URI
https://oasis.postech.ac.kr/handle/2014.oak/96258
DOI
10.1109/APCCAS.2016.7804017
Article Type
Article
Citation
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, page. 514 - 517, 2017-01
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김영환KIM, YOUNG HWAN
Dept of Electrical Enginrg
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