Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
SCIE
SCOPUS
- Title
- Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
- Authors
- Kim, Sangmin; KANG, SEOKHYEONG; Shin, Youngsoo
- Date Issued
- 2016-07
- Publisher
- ASSOC COMPUTING MACHINERY
- Abstract
- A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/96285
- DOI
- 10.1145/2856032
- ISSN
- 1084-4309
- Article Type
- Article
- Citation
- ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, vol. 21, no. 3, 2016-07
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- There are no files associated with this item.
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