Wakeup scheduling and its buffered tree synthesis for power gating circuits

Abstract

Power gating circuit suffers from large amount of rush current during wakeup, especially when all switch cells are turned on simultaneously. If each switch cell is turned on at a different time, rush current can be reduced. It is shown in this paper that rush current can be reduced even more if signal transition time (or signal slew) to each switch cell is adjusted. We define wakeup scheduling as to determine turn-on time and signal slew of each switch cell; the goal is to minimize wakeup delay while keeping rush current below the maximum value that is allowed. The determined turn-on time and signal slew are implemented using a buffered tree. The wakeup scheduling and buffered tree construction are integrated into a design flow. To adapt to process variation, we use adjustable delay buffers in the wakeup network. We also apply grid-based design flow and use Schmitt triggers to implement large designs. Experiments in an industrial 1.1V, 32-nm technology demonstrate that the wakeup delay is reduced by 12% on average of example circuits compared with turn-on scheduling. HighlightsWe determine the signal slew and turn-on time of each footer cell to minimize wakeup delay while rush current constraint is respected.We implement the determined turn-on time and signal slew using a buffered tree.We propose a variation-adaptive design flow that uses adjustable delay buffers to satisfy rush current constraint.Experiments demonstrate that the wakeup delay is reduced compared with turn-on scheduling.