Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study
- Title
- Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study
- Authors
- Kim, Seungwon; KANG, SEOKHYEONG
- Date Issued
- 2018-03-22
- Publisher
- IEEE
- Abstract
- The power integrity of high-speed interfaces is an increasingly important issue in mobile memory systems. However, because of complicated design variations such as adjacent VDD domain coupling, conventional case-specific modeling is limited in analyzing trends in results from parametric variations. Moreover, conventional industrial methods can be simulated only after the design layout is completed and it requires a lot of back-annotation processes, which result in delayed delays time to market. In this paper, we propose a chip-package-PCB coanalysis methodology applied to our multi-domain high-speed memory system model with a current generation method. Our proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPPDR4 environment.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/98325
- Article Type
- Conference
- Citation
- Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-03-22
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- There are no files associated with this item.
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