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dc.contributor.authorLee, Jaemin-
dc.contributor.authorKim, Sunmean-
dc.contributor.authorKim, Youngmin-
dc.contributor.authorKANG, SEOKHYEONG-
dc.date.accessioned2019-04-08T09:13:22Z-
dc.date.available2019-04-08T09:13:22Z-
dc.date.created2019-03-12-
dc.date.issued2016-11-27-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/98525-
dc.publisherIEEE/ IEIE-
dc.relation.isPartOfInternational Conference on Consumer Electronics (ICCE) Asia-
dc.relation.isPartOfInternational Conference on Consumer Electronics (ICCE) Asia-
dc.titleA Novel Design Methodology for Error-resilient Circuits in Near-threshold Computing-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitationInternational Conference on Consumer Electronics (ICCE) Asia-
dc.citation.conferenceDate2016-11-26-
dc.citation.conferencePlaceKO-
dc.citation.titleInternational Conference on Consumer Electronics (ICCE) Asia-
dc.contributor.affiliatedAuthorKANG, SEOKHYEONG-
dc.description.journalClass1-
dc.description.journalClass1-

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