DC Field | Value | Language |
---|---|---|
dc.contributor.author | Koo, J. | - |
dc.contributor.author | Kim, B. | - |
dc.contributor.author | Park, H.-J. | - |
dc.contributor.author | Sim, J.-Y. | - |
dc.date.accessioned | 2019-11-29T05:10:08Z | - |
dc.date.available | 2019-11-29T05:10:08Z | - |
dc.date.created | 2019-07-25 | - |
dc.date.issued | 2019-08 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/99937 | - |
dc.description.abstract | This paper presents a low power and low noise quadrature RC oscillator based on a frequency locked loop. Voltage swing control of each of the two sub-oscillators reduces the effect of 1/f noise on the accumulated jitter. In addition, the use of quadrature phases greatly relieves timing constraints of sampling operations and helps the reduction of power consumption. With a discrete-time modeling of the quadrature oscillator, noise analysis is also provided for quantitative estimation of the circuit-driven effects on the phase noise. The proposed oscillator is fabricated using 180-nm CMOS process in an active area of 0.058mm(2). The measurement shows a period jitter of 0.047% and a standard deviation of 0.94% in untrimmed frequency (444.9kHz) in a wafer. The oscillator achieves a figure-of-merit of 155 dBc/Hz at 100 Hz offset frequency. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.title | A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSI.2019.2906359 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.66, no.8, pp.3077 - 3088 | - |
dc.identifier.wosid | 000474599000022 | - |
dc.citation.endPage | 3088 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 3077 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 66 | - |
dc.contributor.affiliatedAuthor | Koo, J. | - |
dc.contributor.affiliatedAuthor | Kim, B. | - |
dc.contributor.affiliatedAuthor | Park, H.-J. | - |
dc.contributor.affiliatedAuthor | Sim, J.-Y. | - |
dc.identifier.scopusid | 2-s2.0-85068710264 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | Frequency stability | - |
dc.subject.keywordPlus | Jitter | - |
dc.subject.keywordPlus | Locks (fasteners) | - |
dc.subject.keywordPlus | Noise abatement | - |
dc.subject.keywordPlus | Oscillators (electronic) | - |
dc.subject.keywordPlus | Relaxation oscillators | - |
dc.subject.keywordPlus | Accumulated jitter | - |
dc.subject.keywordPlus | Discrete-time model | - |
dc.subject.keywordPlus | Frequency locked loops | - |
dc.subject.keywordPlus | Offset compensation | - |
dc.subject.keywordPlus | Offset frequencies | - |
dc.subject.keywordPlus | Quadrature oscillator | - |
dc.subject.keywordPlus | Quantitative estimation | - |
dc.subject.keywordPlus | Timing constraints | - |
dc.subject.keywordPlus | Phase noise | - |
dc.subject.keywordAuthor | frequency locked loop (FLL) | - |
dc.subject.keywordAuthor | frequency stability | - |
dc.subject.keywordAuthor | offset compensation | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | Relaxation oscillator | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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