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Conference

A Pipeline Architecture with 1-Cycle Timing Error Correction for Low Voltage Operations

IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), page. 199 - 204, 2013-09-05

Conference

Power Minimization of Pipeline Architecture through 1-Cycle Error Correction and Voltage Scaling

IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC), page. 179 - 184, 2014-01-21

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