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A Pipeline Architecture with 1-Cycle Timing Error Correction for Low Voltage Operations
- Title
- A Pipeline Architecture with 1-Cycle Timing Error Correction for Low Voltage Operations
- Authors
- 김재준; 신인섭; Yu-Shiang Lin; 신영수
- Date Issued
- 2013-09-05
- Publisher
- IEEE/ACM
- Article Type
- Conference
- Citation
- IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), page. 199 - 204, 2013-09-05
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Related Researcher
- 김재준KIM, JAE JOON
- Dept. Convergence IT Engineering