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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김재준 | - |
| dc.contributor.author | 신인섭 | - |
| dc.contributor.author | Yu-Shiang Lin | - |
| dc.contributor.author | 신영수 | - |
| dc.date.accessioned | 2018-06-18T08:49:12Z | - |
| dc.date.available | 2018-06-18T08:49:12Z | - |
| dc.date.created | 2013-12-25 | - |
| dc.date.issued | 2013-09-05 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/65012 | - |
| dc.publisher | IEEE/ACM | - |
| dc.relation.isPartOf | IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) | - |
| dc.relation.isPartOf | PROCEEDING OF ISLPED | - |
| dc.title | A Pipeline Architecture with 1-Cycle Timing Error Correction for Low Voltage Operations | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp.199 - 204 | - |
| dc.citation.conferenceDate | 2013-09-04 | - |
| dc.citation.conferencePlace | CC | - |
| dc.citation.endPage | 204 | - |
| dc.citation.startPage | 199 | - |
| dc.citation.title | IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) | - |
| dc.contributor.affiliatedAuthor | 김재준 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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- 김재준KIM, JAE JOON
- Dept. Convergence IT Engineering