Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application
SCIE
SCOPUS
- Title
- Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application
- Authors
- BAEK, ROCK HYUN; JINSU, JEONG; YOON, JUN SIK; SEUNGHWAN, LEE
- Date Issued
- 2020-02
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- Excess source and drain (S/D) recess depth (T-SD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I-off, I-on) in three-stacked NS channels and parasitic bottom transistor (tr(pbt)), gate capacitance (C-gg), intrinsic switching delay time (tau(d)), and static power dissipation (P-static) are investigated quantitatively according to the T-SD variations. More S/D dopants diffuse into the tr(pbt) with the deeper T-SD, so the I-off and I-on increase due to raised current flowing through the tr(pbt). Especially, the I-off of PFETs remarkably increases above the certain T-SD (T-SD;critical) compared to NFETs. Furthermore, the I-on contribution of each channels having the T-SD;critical is the largest at the top NS channel and the tr(pbt) has the ignorable I-on contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) Ion contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C-gg also increases with the deeper T-SD by increasing parasitic capacitance, but fortunately, the tau(d) decreases simultaneously due to the larger increasing rate of the I-on than that of the C-gg for all SoC applications. However, the P-static enormously increases with the deeper T-SD, and low power application is the most sensitive to the TSD variations among the SoC applications. Comprehensive analysis of the inevitable tr(pbt) effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/101318
- DOI
- 10.1109/ACCESS.2020.2975017
- ISSN
- 2169-3536
- Article Type
- Article
- Citation
- IEEE ACCESS, vol. 8, page. 35873 - 35881, 2020-02
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- There are no files associated with this item.
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