DC Field | Value | Language |
---|---|---|
dc.contributor.author | KIM, SEYOUNG | - |
dc.date.accessioned | 2020-04-14T01:53:30Z | - |
dc.date.available | 2020-04-14T01:53:30Z | - |
dc.date.created | 2020-04-13 | - |
dc.date.issued | 2017-08-08 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/103420 | - |
dc.description.abstract | Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training. | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.relation.isPartOf | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems | - |
dc.relation.isPartOf | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems | - |
dc.title | Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems | - |
dc.citation.conferenceDate | 2017-08-06 | - |
dc.citation.conferencePlace | US | - |
dc.citation.title | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems | - |
dc.contributor.affiliatedAuthor | KIM, SEYOUNG | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
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