DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Junjong | - |
dc.contributor.author | Yoon, Jun-Sik | - |
dc.contributor.author | Lee, Seunghwan | - |
dc.contributor.author | Jeong, Jinsu | - |
dc.contributor.author | Baek, Rock-Hyun | - |
dc.date.accessioned | 2021-06-13T03:50:31Z | - |
dc.date.available | 2021-06-13T03:50:31Z | - |
dc.date.created | 2021-04-07 | - |
dc.date.issued | 2021-03 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/106686 | - |
dc.description.abstract | In this article, we analyzed the stability, power, performance, and area of 6T-SRAMs using a promising scaling booster, i.e., source/drain patterning (SDP) scheme for the 3-nm technology node based on 3-D TCAD simulation. SDP scheme allows to decrease the spacing between transistors by downsizing the source/drain epitaxy. Proposed 5-nm and 3-nm SDP-SRAM (SDP-SRAM(5) and SDP-SRAM(3)) are compared with conventional 5-nm node SRAM (Conv-SRAM(5)), quantitatively. Unlike a Conv-SRAM(5), SDP-SRAMs have more design margins according to the two fin position parameters: fin location adjustment (FLA) and separation pitch adjustment (SPA). The optimized layout has the maximum FLA by significantly decreasing the back-end-of-line (BEOL) bitline and internal node capacitance. Read and write static noise margins were comparable (< 10 mV) between the SDP-SRAM and Conv-SRAM. The SDP-SRAM(5) improved the read access time 18% compared to the Conv-SRAM(5) in low-power (LP) applications, but the SDP-SRAM(3) degraded it by 11% in high-performance (HP) applications because of the narrow M2 pitch. Both the SDP-SRAM(5) and SDP-SRAM(3) improved write access time about 10% compared to a Conv-SRAM(5) in LP applications. The cell area of the SDP-SRAM(3) decreased about 0.64 times compared to a Conv-SRAM(5) without severe degradation of performance. The SDP scheme provides flexible layout designs enabling a high-density SRAM, promising for 3-nm node logic applications. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.title | TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TED.2021.3053508 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.3, pp.1031 - 1036 | - |
dc.identifier.wosid | 000622100700014 | - |
dc.citation.endPage | 1036 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 1031 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 68 | - |
dc.contributor.affiliatedAuthor | Lee, Junjong | - |
dc.contributor.affiliatedAuthor | Yoon, Jun-Sik | - |
dc.contributor.affiliatedAuthor | Lee, Seunghwan | - |
dc.contributor.affiliatedAuthor | Jeong, Jinsu | - |
dc.contributor.affiliatedAuthor | Baek, Rock-Hyun | - |
dc.identifier.scopusid | 2-s2.0-85100454823 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Metals | - |
dc.subject.keywordAuthor | Capacitance | - |
dc.subject.keywordAuthor | Layout | - |
dc.subject.keywordAuthor | Epitaxial growth | - |
dc.subject.keywordAuthor | Radio access technologies | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | 3-D-TCAD | - |
dc.subject.keywordAuthor | 3-nm node | - |
dc.subject.keywordAuthor | 5-nm node | - |
dc.subject.keywordAuthor | 6T-SRAM | - |
dc.subject.keywordAuthor | access time | - |
dc.subject.keywordAuthor | back-end-of-line (BEOL) | - |
dc.subject.keywordAuthor | FinFETs (FFs) | - |
dc.subject.keywordAuthor | mixed-mode simulation | - |
dc.subject.keywordAuthor | power performance and area | - |
dc.subject.keywordAuthor | source | - |
dc.subject.keywordAuthor | drain patterning (SDP) | - |
dc.subject.keywordAuthor | static noise margin | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
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