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2-Bit-per-Cell RRAM based In-Memory Computing for Area-/Energy-Efficient Deep Learning SCOPUS

Title
2-Bit-per-Cell RRAM based In-Memory Computing for Area-/Energy-Efficient Deep Learning
Authors
He, W.Yin, S.Kim, Y.Sun, X.Sun, X.Kim, J.Yu, S.Seo, J.
Date Issued
2020-07
Publisher
Institute of Electrical and Electronics Engineers Inc.
Abstract
In-memory computing (IMC) has emerged as a promising technique for enhancing energy-efficiency of deep neural networks (DNN). While embedded non-volatile memory such as resistive RAM (RRAM) is a good alternative to SRAM/ DRAM for IMC owing to high density, low leakage, and non-destructive read, most prior works have not demonstrated using multi-level RRAM devices for array-level IMC operations. In this work, we present an IMC prototype with 2-bit-per-cell RRAM devices for area-/energy-efficient DNN inference. Optimizations on four-level conductance distribution and peripheral circuits with input-splitting scheme have been performed, enabling high DNN accuracy and low area/energy consumption. The prototype chip that monolithically integrated 90nm CMOS and 2-bit-per-cell RRAM array achieves 87% (83%) CIFAR-10 accuracy and 25 (51) TOPS/W energy-efficiency at 1.2 V (0.9 V) supply. At 1.2V, a stable accuracy of 87% is maintained throughout 108 hours. IEEE
URI
https://oasis.postech.ac.kr/handle/2014.oak/106914
DOI
10.1109/LSSC.2020.3010795
ISSN
2573-9603
Article Type
Article
Citation
IEEE Solid-State Circuits Letters, vol. 3, page. 194 - 197, 2020-07
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김재준KIM, JAE JOON
Dept. Convergence IT Engineering
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