FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks
- Title
- FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks
- Authors
- CHANGHYEON, KIMCHANGHYEON; RIM, DONGYOUNG; JEONGWON, CHOE; KAM, DONG YUN; Park, Giyoon; Kim, Seokki; LEE, YOUNGJOO
- Date Issued
- 2021-11-08
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than 10^{-6}, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/110209
- Article Type
- Conference
- Citation
- 2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, 2021-11-08
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- There are no files associated with this item.
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