An investigation on grain-boundary trap properties using staircase charge-pumping technique in polysilicon thin-film transistors

Abstract

The well-known staircase charge-pumping (SCP) technique was adopted to characterize the grain-boundary trap state in the polysilicon thin-film transistor. By measuring the SCP current for various step times, we can obtain the trap state energy distributions at grain boundaries for different (electron or hole emission) time constant windows between submicrosecond to millisecond. It is confirmed with the SCP technique that a quantity of the deep trap state at the grain boundaries is mainly affected by the size of the grains and, as compared to the interface trap state of the bulk metal-oxide semiconductor field effect transistors, the grain-boundary trap states of the polysilicon thin-film transistors have the broader time constant, up to 3 ms.