Nanowire Diameter Dependency of the Variability in n/p Silicon Nanowire FETs With Ultrashort Gate Length of 15 nm

Abstract

IEEEIn this study, the nanowire diameter (<inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula>) dependency of the variability of n/p silicon nanowire field-effect transistors was experimentally investigated in silicon nanowire field-effect transistors (SNWFETs) with an ultrashort gate length (<inline-formula> <tex-math notation="LaTeX">$\textit{L}_{\text{G}}$</tex-math> </inline-formula>) of 15 nm and <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> of 7, 9, and 12 nm. The ON current at linear region (<inline-formula> <tex-math notation="LaTeX">$\textit{I}_{\text{on\_lin}}$</tex-math> </inline-formula>) variation was decomposed into three performance parameters&#x2014;threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula>), carrier mobility (<inline-formula> <tex-math notation="LaTeX">$\mu_{\text{0}}$</tex-math> </inline-formula>), and source/drain series resistance (<inline-formula> <tex-math notation="LaTeX">$\textit{R}_{\text{SD}}$</tex-math> </inline-formula>)&#x2014;using the error propagation equation. The results indicated that a moderate decrease in <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> improves gate controllability, reducing variation in <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\textit{I}_{\text{on\_lin}}$</tex-math> </inline-formula>. However, when <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> was excessively reduced, the <inline-formula> <tex-math notation="LaTeX">$\textit{I}_{\text{on\_lin}}$</tex-math> </inline-formula> variation increased because random variations and quantum confinement (QC) effects caused fluctuations in <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\textit{R}_{\text{SD}}$</tex-math> </inline-formula>. The effect of gate-controllability improvement was dominant in p-SNWFETs, whereas the effect of QC and <inline-formula> <tex-math notation="LaTeX">$\textit{R}_{\text{SD}}$</tex-math> </inline-formula> variation was dominant in n-SNWFETs. Consequently, the <inline-formula> <tex-math notation="LaTeX">$\textit{R}_{\text{SD}}$</tex-math> </inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula>) contribution to <inline-formula> <tex-math notation="LaTeX">$\textit{I}_{\text{on\_lin}}$</tex-math> </inline-formula> variation rapidly increased (decreased) from 15% (64%) at <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> of 7 nm to 54% (41%) at <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> of 12 nm in n-(p-)SNWFETs. Overall, the <inline-formula> <tex-math notation="LaTeX">$\textit{I}_{\text{on\_lin}}$</tex-math> </inline-formula> variation was smallest at <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> of 9 nm (7 nm) in n-(p-) SNWFET. The optimal <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> occurred at a point where <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{th}}$</tex-math> </inline-formula> and <inline-formula> <tex-math notation="LaTeX">$\textit{R}_{\text{SD}}$</tex-math> </inline-formula> variations were balanced, and this point depended on the dopant profile of SNWFETs. This suggests that the variability improvement strategy should differ depending on the <inline-formula> <tex-math notation="LaTeX">$\textit{D}_{\text{NW}}$</tex-math> </inline-formula> and dopant profile of ultrascaled channel FETs.