A Phase-Change RAM Aware Cache Replacement Policy

Abstract

Phase-change RAM (PRAM) is considered to be a practical solution to address the limitations of current main memory, DRAM, e.g., power consumption and scaling limit. However, PRAM suffers from its own limitations especially due to high write latency/power and poor write endurance. Thus, it is critical to minimize writes for its widespread adoptions in the main memory. In this paper, we propose a novel cache replacement policy which exploits write coalescing and bit difference in order to minimize PRAM writes. The design-time application-specific policy takes into account both write-coalescing capability and recency in prioritizing cache lines while meeting the given performance requirement. The runtime method adjusts PRAM-awareness level as application's behavior. Experimental results show that the application-specific optimizations of proposed cache architecture give average 16.7% more reductions in PRAM writes than the existing N-chance policy while satisfying given miss ratio bound. They also show that the proposed cache replacement policy with runtime adjustment give average 11.2% more reductions in PRAM writes than N-chance policy with fix N value.