Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability
SCIE
SCOPUS
- Title
- Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability
- Authors
- Kim, C; Kim, H; Kang, B
- Date Issued
- 2014-11
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Abstract
- This paper investigates voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t(L) = 1.64 x 10(10) s, which agreed well with the t(L) = 1.92 x 10(10) s measured at low gate stress voltage, whereas the conventional model overestimates t(L) by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t(L) of high-k nMOSFETs. (C) 2014 Elsevier Ltd. All rights reserved.
- Keywords
- High-k dielectrics; Positive bias temperature instability (PBTI); Electron trap; FN stress; Shallow traps; GATE DIELECTRIC STACKS; INTERFACE TRAPS; MECHANISM; STRESS
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/14061
- DOI
- 10.1016/J.MICROREL.2014.06.001
- ISSN
- 0026-2714
- Article Type
- Article
- Citation
- MICROELECTRONICS RELIABILITY, vol. 54, no. 11, page. 2383 - 2387, 2014-11
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