Electrical characteristics of 20-nm junctionless Si nanowire transistors

Abstract

We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 urn showed excellent electrical characteristics with a high I-on/I-off ratio (>10(6)), good subthreshold slope (similar to 79 mV/dec), and low drain-induced barrier lowering (similar to 10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes. (C) 2012 Elsevier Ltd. All rights reserved.