VLSI architecture for SAR data compression
SCIE
SCOPUS
- Title
- VLSI architecture for SAR data compression
- Authors
- Jeong, H; Park, JH; Ryu, HY; Kwon, JB; Oh, Y
- Date Issued
- 2002-04
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- As a step towards a real-time signal aperture radar (SAR) correlator, custom very large scale integration (VLSI) architectures are developed. Considering the extremely short word length of the data, we derive three architectures with massive parallelism in bit space. Unlike frequency methods, no degradation is introduced during convolution. Optimized for time and space, they are highly suited to VLSI implementation, and a small architecture with 80 taps operating at 10 MHz has been built using an FPGA.
- Keywords
- MIGRATION; COMPENSATION
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/19046
- DOI
- 10.1109/TAES.2002.1008977
- ISSN
- 0018-9251
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, vol. 38, no. 2, page. 427 - 440, 2002-04
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- There are no files associated with this item.
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