Design considerations for low-power single-electron transistor logic circuits
SCIE
SCOPUS
- Title
- Design considerations for low-power single-electron transistor logic circuits
- Authors
- Jeong, MY; Lee, BH; Jeong, YH
- Date Issued
- 2001-03
- Publisher
- INST PURE APPLIED PHYSICS
- Abstract
- We have investigated design considerations for low-power single-electron transistor (SET) logic circuits. Supply-voltage scaling is introduced as a method for reducing the power consumption of SET circuits. A detailed analysis of the effects of supply-voltage scaling is given on the basis of the behavior of a complementary capacitively coupled SET inverter circuit. It has been shown that the hysteresis caused by the supply-voltage-dependent threshold voltage of a SET quickly disappears as the temperature rises, and does not ruin the desired inverting operation at a practical operation temperature. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. From the results of power-delay product and delay time. it has been shown that the supply-voltage scaling should be carried out within 20% of maximum supply-voltage to maintain overall circuit performance.
- Keywords
- single-electron transistor; single-electron transistor logic; Coulomb blockade; power consumption; GATE
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/19423
- DOI
- 10.1143/JJAP.40.2054
- ISSN
- 0021-4922
- Article Type
- Article
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, vol. 40, no. 3B, page. 2054 - 2057, 2001-03
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.