A digital CMOS PWCL with fixed-delay rising edge and digital stability control

Abstract

A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 +/- 0.4%. The chip was fabricated by using a 0.25-mu m CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mu m x 250 mu m and 18 mW at an input clock frequency of 1.0 GHz, respectively.