Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics

Abstract

Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) height influenced off-state and on-state performance variations, respectively, but slightly on RC delay variations. Fin width variations induced off-state performance and RC delay variations critically due to the fluctuation of short channel effects. But, fin height variations affected them slightly due to the preserved gate-to-channel controllability and the buffered effects by varying drain currents and gate capacitances in the same direction. Gate length, spacer length, and S/D length variations influenced dc/ac performance variations severely; 2-nm-length changes were barely acceptable to satisfy 10% RC delay margin. Thus, the process-induced variability parameters, including fin width, gate length, spacer length, and S/D length, should be controlled tightly under a few nanometers to reduce dc/ac performance variations of the FinFETs.