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Cited 3 time in webofscience Cited 5 time in scopus
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Memory-reduced turbo decoding architecture using NII metric compression SCIE SCOPUS

Title
Memory-reduced turbo decoding architecture using NII metric compression
Authors
Lee, YLi, MVan der Perre, L
Date Issued
2016-02
Publisher
IEEE
Abstract
This brief proposes a new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores only the range of state metrics as well as two indexes of the maximum and minimum values, while the previous compression methods have to store all of the state metrics for initializing the following iteration. We also present a hardware-friendly recovery strategy, which can be implemented by simple multiplexing networks. Compared to the previous work, as a result, the proposed compression method reduces the required storage bits by 30% while providing the acceptable error-correcting performance in practice.
URI
https://oasis.postech.ac.kr/handle/2014.oak/37531
DOI
10.1109/TCSII.2015.2483361
ISSN
1549-7747
Article Type
Article
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 63, no. 2, page. 211 - 215, 2016-02
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이영주LEE, YOUNGJOO
Dept of Electrical Enginrg
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